Interconnect Analysis of Spatial Decomposition of Boolean Functions for Predictable Nanotechnologies

This paper addresses the interconnect problem of representation of logic networks in spatial dimensions. Interest to spatial interconnect is motivated by the advent in nanotechnologies and attempts to evaluate and explore the appropriate nanoscale architectures. It have been shown in our previous study that 3D logic network with target topology can be designed by replacing each elementary logic block in a network by its 3D equivalent. In this paper, we solve the problem of partitioning of these 3D blocks over constraints of logic function interconnect and hypercube-like topology. This problem is motivated by the fact that nanotechnologies are sometime critical to the type of this interconnect. We found that decomposition techniques are useful to this solution because provide possibilities to chose a logic functions for assembling decomposed sub-networks.